As a computing device, an integrated circuit (IC) is often evaluated by how fast it can process data. The more data an IC is able to process in a given amount of time, the better performing the IC is generally considered to be. There are several techniques a designer of an IC can employ to increase the performance of an IC from an original design. One of these techniques is to increase the frequency of the clock driving the IC or a particular logic block in the IC. Increased clock speed enables additional data to be processed by having additional clock transitions during the same interval of time.
However, increasing the frequency of the clock has many disadvantages. A higher frequency clock necessarily leads to more signal switching, which leads to higher power consumption and more noise. Even if higher power consumption is acceptable or if a faster performing semiconductor technology is available, the maximum frequency of a clock in the IC is still constrained by the physical limitations of the IC (e.g., propagation delays and parasitic elements). In other words, it is often impossible to achieve a desired performance gain by increasing clock frequency alone.
In order to achieve the desired performance gain without increasing clock speed, an IC designer can use additional areas of the chip to modify a logic block or a subset of the circuits in the IC for parallel processing. For logic blocks with structures that are highly regular (e.g., adders and multipliers), this is a straightforward task of devising repetitive, parallel data paths. For logic blocks with structures that are irregular (e.g., control logic), designing additional circuitry for achieving performance gain (or conversely for reducing clock speed) usually requires a great deal of engineering effort to devise specialized schemes such as breaking logic into pipeline stages. Such methods are usually ad hoc and cannot always retain the functionality and the latency of the original design. Some such methods may also require alteration of the interface between the logic block and the rest of the circuit, adding further complexity to the IC design process.
There is therefore a need for a method that improves the performance of an original design of an IC by using additional circuitry, a method that predictably produces a new design of the IC that retains the functionality, latency, bandwidth and interface of the original design.